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EDA Confidential
TSMC's Dr. Shang-Yi Chiang by Peggy Aycinena April 14, 2010 Dr. Shang-Yi Chiang is Senior Vice President of Research and Development at TSMC. Dr. Chiang joined TSMC in 1997, retired briefly in 2006, and returned in September 2009 to resume his position leading R&D at the company. Prior to his many years at TSMC, Chiang spent 17 years at Hewlett Packard, and before that was at Texas Instruments and ITT Corp. I had a chance to interview Dr. Chiang on the afternoon of April 13th in San Jose during the all-day TSMC Technology Symposium at the San Jose Convention Center. Earlier in the day, Dr. Chaing delivered the second keynote of four keynotes during the Symposium's morning session. TSMC Chairman and CEO Dr. Morris Chan had offered the first keynote. My conversation with Dr. Chiang began with questions arising from his morning talk.
Q – You mentioned in your morning talk that, because speed, power, and cost are often in conflict during design, collaborating with your customers at early stages in the design would allow for optimal tradeoffs. How early is early enough? Dr. Chiang – Dr. Chan noted in his keynote this morning that he had requested customers begin to work with TSMC on the move to 40 nanometers at early stages in their designs. Now at 28 nanometers, he is asking customers to start working with us even before they begin their design. Q – Is that really possible, given designers are very busy wrestling with the day-to-day issues of their projects. Dr. Chiang – It has happened many times in the industry, that as people become dedicated to working out future generations of technology they have understood the importance of looking ahead. Right now, we are in production at 40 nanometers, but we have many people in the company working at 28 nanometers and 20 nanometers, as well. As you say, however, out in the design community there are very few designers looking to the next generation. Typically, we have observed that when designers finish their current design, only then do they look forward to the next process node. Our challenge is to talk to customers and convince them to look at the issues of the next process node earlier, even while they're designing to the previous node. Fortunately, a few of our key major customers have dedicated teams in-house who focus totally on working on the next generation design issues. Unfortunately, as you say, the smaller customers may not be able to afford that effort. Q – You also mentioned this morning that the move to high-k metal gates at 28 nanometers was very difficult. What was the principle challenge there? Dr. Chiang – High-k metal gates represent a new material. Typically when the industry introduces a new material, it takes 10 years to mature, 10 years to go into full production. That is why people are sometimes afraid to deal with a new material, which is not surprising. This move meant changing the gate oxide, which is essentially at the very heart of the transistor. It's the most important part of the transistor. With this move, we are replacing that heart. In reality, the gate structure is very complicated and we are adding a lot more steps in that complexity, in the manufacturing. It has been very difficult. Q – How do you organize the research and development effort at the company to coordinate this kind of change? Do you partner at the early stages with universities to explore various options? Dr. Chiang – We divide the research effort into three phases. Phase 1 is the exploratory phase, and we do engage with some universities in this phase. In Phase 1, the research may not have any particular purpose in mind. We may hope that it will prove useful one day, but it is seen as basic research at that phase and may take place as early as 4-to-6 years before any production use is made of the results. Phase 2 in the research effort is called path finding and usually takes place 2-to-4 years prior to production. In the case of high-k metal gates, we thought there might be 3 possible ways to go, and we tried all 3 of them before we nailed down which one to use. However, it is not unusual in any path finding phase to develop three different options. We often find that the first one doesn't work at all, that the second one is okay, but not as good as the third option – the one we decide to go with. Often, we will put option 2 to the side and look at it the next time we do research into this particular topic. Phase 3 of the R&D, implementation, takes place over the last 2 years before production. At that point, all of the technical issues are settled and the effort surrounds pushing the technology to yield. Q – This morning you discussed the differences between your 28 nanometer low power offering, 28LP, and 28 nanometer high performance, 28HP. Which was more difficult to nail down? Dr. Chiang – The low power and high performance offerings were of equivalent difficulty, given that they have the equivalent dielectric issues. For 28HP, the dielectric is only 13 angstroms think and, for low power, is only 14.5 angstroms. For both the channel lengths are only 2 nanometers, so the difficulties are pretty similar between the two. Q – Is it possible to have both low power and high performance at 28 nanometers, if the technical issues between the two offerings are so small? Dr. Chiang – As my slides this morning indicated, 28HP covers high performance, 28LP covers low power, and 28HPM gives you high performance mobile. If you're looking for the best of both, you need to use the 28HPM. Q – Speaking of mobile, if I had $100 million to invest, should I invest in next-generation battery technology, or the technicolor needed to develop the next process node? Dr. Chiang – [Laughing] I guess it would depend on who you ask. Certainly, if you ask people in the semiconductor industry, the answer is simple – invest in 20 nanometers! As you shrink the process node, the shrinkage will help you reduce power. Today, it may not seem to happen that way because when we shrink the node, functionally the device becomes more complicated and the power may not come down. But, in reality, if you add more functionality and do not increase the speed, shrinkage will improve the power usage, and so you're better to invest there, rather than in the batteries. Q – How will you make the decision to skip 22 nanometers, and go straight from 28 nanometers to 20 nanometers? Dr. Chiang – We already have made that decision! We will skip 22 nanometers. [TSMC formally announced the decision during the September 13 Symposium.] From our customers' point of view, they want to maximize the value for their costs. We have very carefully calculated the cost between moving to 22 nanometers and moving to 20, and we know the difference. The value between the two nodes is a 10% improvement in linear dimension, but a 20% improvement in area. However, the bump pad doesn't shrink and the I/O doesn't shrink, so in considering the cost of the move, going to 20 nanometers is a much better decision. Of course, there is always the other issue to consider – the schedule risk. Are we capable of ramping production at 20 nanometers as soon as possible for our customers. If our competitors offer 22 nanometers and offer it soon, our customers are faced with a difficult decision. There is always this risk involved! Q – If you're promising to deliver 20 nanometers soon, however, won't you customers be willing to wait? Dr. Chiang – We see three categories of customers: 1st-wave customers, 2nd-wave, and and 3rd-wave. Our 1st-wave customers jump right to the newest technology, because they have a very good idea of when we'll have that technology ready. We are in constant and close communication with these customers, so they know exactly where we are in the process. They also have confidence that we will do it. If we miss the schedule, of course, they are disappointed. Q – Can you grade the success of these nodes? 90 nanometer, 65 nanometer, 40 nanometer, 28 nanometer? Dr. Chiang – Well, we are only beginning to ramp up 40 nanometers, so it's not quite clear as yet. However, 65 is a very popular node for a good reason. With the move from generation to generation, we do a 70% shrink. In addition, we always put in 2-to-3 new features – more than just the shrink. Those features, those changes may be major or minor. Going from 90 to 65 nanometers, the changes were minor and, therefor, the relative costs for 65 were very competitive. It was a very popular node. Q – From an EDA perspective, what would you like to see the tool vendors offer to make life easier from a manufacturing point of view? Dr. Chiang – Today, the bottleneck in manufacturing is lithography, not design tools. Q – Is it worth noting, however, that EDA vendors have access to the designers early on in the design stage, at that point where you would like to start working with them? Dr. Chiang – It's true, the tool vendors do have access to the designers and, yes, we always have to partner with the tool vendor, the process person, and the designer all together. If we move to something new – if we decide, for instance, that 40 nanometers would be a finFET structure -- then definitely we have to work with the entire design infrastructure. The infrastructure has to be ready before the design can even begin to design a finFET. Q – Do you think the designers will resist the move to FinFETs? Dr. Chiang – Probably not, particularly when they see that have no other choice. Q – You mentioned lithography. Which technology do you predict will be the winner 10 years from today? EUV versus eBeam versus some other technology? Dr. Chiang – TSMC is pushing the lithography road map with multiple partners. Yes, eBeam is fantastic. You can do the integration on the chip at the beginning. At the moment, however, EUV has the most mature infrastructure. Remember that after [dimensions dropped below] 193 nanometers, the industry invested billions of dollars to develop 157 lithography. However, Bernie Meyer son, the industry expert argued that 157 would not work. Instead, he said it would be better to put the lithography in water. He was a single individual, and was able to turn the industry around. The industry abandoned 157 and went to 193 immersion lithography, instead. Q – Given all of the expense of the tools, the dabs, etc. – how are small start-ups, companies with just 2 or 3 engineers, supposed to contemplate innovating on a new design? What can TSMC do to help those types of enterprises? Dr. Chiang – We provide design services, we offer the basic library, and we also offer IP for special technology related to IP. When we offer a new technology, the first thing we do even before we release the technology – we work with at least 2 vendors in each category to prove their tools can work on TSMC technology. To do that, we to set a lot of parameters. The reality, however, is although we work with large companies on new technologies, the huge fabless companies don't need our help. Instead, we do all of this for the purpose of helping this small company you describe. We provide the small companies a lot of support, sometime even making our large customers unhappy in the process. Q – I was impressed during the morning keynotes, with the huge, global vision all of the TSMC speakers seemed to be point to. However, it seems that the road map requires there only be one foundry in the world – one player who coordinates all of the partners up and down the semiconductor supply chain. How would you respond to that impression? Dr. Chiang – Yes, it does seem like it would be easier for everyone if everybody were in the same company, and we could all think together. But today, in the foundry business domain, there are enough business opportunities for everyone – for tool vendors, for foundries, for designer. There are definitely enough opportunities! It is important to realize that you have to work together, we all have to work together, to be successful. That is the message of collaboration that we are emphasizing today, all day. ___________________________________________________________ Peggy Aycinena owns and operates EDA Confidential: Copyright (c) 2010, Peggy Aycinena. All rights reserved. |